The present invention is related to semiconductor memories, especially dynamic random access memory (DRAM) and static random access memory (SRAM). In particular, the present invention relates to a method and apparatus of handling refresh operations in a semiconductor memory such that the refresh operations do not interfere with external access operations.
A conventional DRAM memory cell, which consists of one transistor and one capacitor, is significantly smaller than a conventional SRAM cell, which consists of 4 to 6 transistors. However, data stored in a DRAM cell must be periodically refreshed, while the data stored in an SRAM cell has no such requirement. Each refresh operation of a DRAM cell consumes memory bandwidth. For example, the cycle time of a 100 MHz DRAM array is 10 nsec. In this DRAM array, each external access takes 10 nsec, and each refresh access takes at least 10 nsec. Because an external access and a refresh access can be initiated at the same time, the DRAM array must be able to handle both within the allowable access cycle time so as to prevent the refresh access from interfering with the external access. This limits the minimum external access cycle time to be no less than 20 nsec, with 10 nsec for handling the external access and 10 nsec for handling the refresh access. This is true even though the refresh accesses are performed, on average, at a frequency of 62.5 kHz. As a result, the maximum accessing frequency of the DRAM array must be less than or equal to 50 MHz. Thus, a 100 Mhz DRAM memory array is required to create a device capable of operating at 50 MHz. This is simply not economical.
Previous attempts to use DRAM cells in SRAM applications have been of limited success for various reasons. For example, one such DRAM device has required an external signal to control refresh operations. (See, 131,072-Word by 8-Bit CMOS Pseudo Static RAM, Toshiba Integrated Circuit Technical Data (1996).) Moreover, external accesses to this DRAM device are delayed during the memory refresh operations. As a result, the refresh operations are not transparent and the resulting DRAM device cannot be fully compatible with an SRAM device.
In another prior art scheme, a high-speed SRAM cache is used with a relatively slow DRAM array to speed up the average access time of the memory device. (See, U.S. Pat. No. 5,559,750 by Katsumi Dosaka et al, and xe2x80x9cData Sheet of 16 Mbit Enhanced SDRAM Family 4Mx4, 2Mx8, 1Mx16xe2x80x9d by Enhanced Memory Systems Inc., 1997.) The actual access time of the device varies depending on the cache hit rate. Circuitry is provided to refresh the DRAM cells. However, the refresh operation is not transparent to external accesses. That is, the refresh operations affect the memory access time. Consequently, the device cannot meet the requirement of total deterministic random access time.
Other prior art schemes use multi-banking to reduce the average access time of a DRAM device. Examples of multi-banking schemes are described in xe2x80x9cData sheet, MD904 To MD920, Multi-bank DRAM (MDRAM) 128Kx32 to 656Kx32xe2x80x9d by MoSys Inc., 1996, and in xe2x80x9cAn Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM""sxe2x80x9d by Kazushige Ayukawa et al, IEEE JSSC, vol. 33, No. 5, May 1998, pp. 800-806. These multi-banking schemes do not allow an individual memory bank to delay a refresh cycle.
Another prior art scheme uses a read buffer and a write buffer to take advantage of the sequential or burst nature of an external access. An example of such a prior art scheme is described in U.S. Pat. No. 5,659,515, entitled xe2x80x9cSemiconductor Memory Device Capable of Refresh Operation in Burst Modexe2x80x9d by R. Matsuo and T. Wada. In this scheme, a burst access allows a register to handle the sequential accesses of a transaction while the memory array is being refreshed. However, this scheme does not allow consecutive random accesses. For example, the memory cannot handle a random access per clock cycle.
Another prior art scheme that attempts to completely hide refresh operations in a DRAM cell includes the scheme described in U.S. Pat. No. 5,642,320, entitled xe2x80x9cSelf-Refreshable Dual Port Dynamic CAM Cell and Dynamic CAM Cell Array Refreshing Circuitxe2x80x9d, by H. S. Jang. In this scheme, a second port is added to each of the dynamic memory cells so that refresh can be performed at one port while a normal access is carried out at the other port. The added port essentially doubles the access bandwidth of the memory cell, but at the expense of additional silicon area.
Accordingly, it would be desirable to have a memory device that utilizes area-efficient DRAM cells, and handles the refresh of the DRAM cells in a manner that is completely transparent to an accessing memory client external to the memory device. That is, it would be desirable for the refresh operations to be successfully performed without relying on unused external access time. Stated another way, it would be desirable to have a memory device that allows the use of DRAM cells or other refreshable memory cells for building SRAM compatible devices or other compatible memory devices that do not require refresh.
Accordingly, the present invention provides a memory device that includes a plurality of memory cells that must be periodically refreshed in order to retain data values, and a control circuit for accessing and refreshing the memory cells. In one embodiment, the memory cells are DRAM cells. The control circuit controls the accessing and refreshing of the memory cells such that the refreshing of the memory cells does not interfere with any external access of the memory cells.
The memory cells are arranged in a plurality of independently controlled memory banks. Thus, read, write and refresh operations are independently controlled within each bank. Each of the memory banks is coupled in parallel to a read buffer, such that data read from any one of the memory banks is provided to the read buffer. Each of the memory banks is further coupled in parallel to a write buffer, such that data written to any of the memory banks can be provided from the write buffer.
The control circuit includes an SRAM cache, which has the same configuration as each of the memory banks. A cache read buffer is coupled between an output port of the SRAM cache and the write buffer, thereby facilitating the transfer of data from the SRAM cache to the memory banks. Similarly, a cache write buffer is coupled between an input port of the SRAM cache and the read buffer, thereby facilitating the transfer of data from the memory banks to the SRAM cache. The cache read buffer and the cache write buffer are further coupled to an external data bus. The SRAM cache provides an interface between the external data bus and the memory banks. The SRAM cache implements a write-back policy, such that all write data is initially written to the SRAM cache before being written to the memory banks, and all read data provided to the external data bus is stored in the SRAM cache. In one embodiment, the SRAM cache is configured as a direct map cache. The SRAM cache is selected to have a capacity sufficient to ensure that each of the memory banks is refreshed properly within a predetermined refresh period. That is, even under the worst case cache-thrashing conditions, the required refresh operations will always be performed without delaying any external accesses to the memory device.
In one embodiment, the cache write-back policy is carried out as follows. First, a current access address received on the external data bus is compared with a cached address stored in the SRAM cache to determine whether a cache miss or a cache hit occurs. When a cache hit occurs, the requested data is either read from the SRAM cache (for a read access) or written to the SRAM cache (for a write access). Thus, the memory banks are not accessed when a cache hit occurs. Refresh operations can therefore be performed within the memory banks when a cache hit occurs, when a refresh request is pending. Because the memory banks are independently controlled, all of the memory banks can be simultaneously refreshed during a cache hit. Alternatively, predetermined sets of the memory banks can be simultaneously refreshed.
When a cache miss occurs, a determination is made as to whether the cache entry associated with the cached address contains data that has been modified. That is, a determination is made as to whether the cache entry contains the same data as the associated memory bank. A determination is also made as to whether the current access is a read access or a write access.
If a cache miss occurs and the data in the cache entry has not been modified, then processing proceeds as follows for read and write accesses. For a read access, the desired data is read from the memory bank associated with the current access address. This data is simultaneously provided to the external data bus and written to the SRAM cache, thereby overwriting the original cache entry. Because the original cache entry did not contain modified data, there is no need to write back the original cache entry under these conditions. For a write access, a portion of the original cache entry is overwritten with the new data associated with the write access. The remaining portion of the original cache entry is overwritten with data retrieved from the memory bank identified by the current access address. Again, because the original cache entry did not contain modified data, there is no need to write back the original cache entry under these conditions. Note that only one memory bank needs to be accessed during a cache miss when the cache entry does not contain modified data.
If a cache miss occurs and the data in the cache entry has been modified, processing proceeds as follows. First, the cache entry is written back to the memory bank from which it originated. This write-back operation transfers the cache entry from the SRAM cache, through the cache read buffer and the write buffer, to the memory bank. At the same time, a new cache entry is read from a memory bank identified by the external access address. This new cache entry is written to the SRAM cache. This operation transfers the new cache entry from the memory bank, through the read buffer and the cache write buffer, to the SRAM cache. If the current access is a read access, then the new cache entry is simultaneously routed to the external data bus. If the access is a write access, then the write data is written to the SRAM cache along with the rest of the data of the new cache entry.
Note that only one or two memory banks are accessed during a cache miss. Thus, all of the other memory banks can be refreshed during a cache miss operation. Also note that because read and write accesses to the memory banks are performed simultaneously, each access can be completed during a single clock period. As a result, the memory device is accessed in the same manner as a conventional SRAM.
In accordance with another embodiment, the present invention provides a memory device that includes a plurality of memory cells that must be periodically refreshed in order to retain data values. The memory cells are arranged to form a plurality of memory banks, each arranged in rows and columns. A memory controller is provided to control the accessing and refreshing of the memory cells, such that the refreshing of the memory cells does not interfere with any external read accesses to the memory cells. A read buffer is coupled to the banks and the memory controller. The read buffer has a capacity greater than or equal to the capacity of a memory bank minus one row of memory cells. The read buffer can be constructed from either SRAM cells or DRAM cells.
In one embodiment, the memory controller operates as follows. If an external read access misses the read buffer, the memory controller causes a data value to be read from the memory bank that is addressed by the read access. The memory controller further causes this data value to be written to the read buffer during the same clock cycle. If an external write access hits the read buffer, the memory controller causes the data value associated with the write access to be written to the read buffer. If an external read access hits the read buffer, the memory controller causes the data value requested by the read access to be read from the read buffer.
If the read buffer is constructed using DRAM cells, the read buffer will have to be refreshed. In accordance with one embodiment, the memory controller is configured to enable a refresh access to the read buffer only if there is no pending access to the read buffer.
In accordance with another embodiment, the present invention provides a memory device that includes a plurality of memory cells that must be periodically refreshed in order to retain data values. The memory cells are arranged to form a plurality of memory banks, each arranged in rows and columns. A memory controller is provided to control the accessing and refreshing of the memory cells, such that the refreshing of the memory cells does not interfere with any external write accesses to the memory cells. A write buffer is coupled to the memory banks and the memory controller. The write buffer has a capacity greater than or equal to the capacity of a memory bank minus one row of memory cells. The write buffer can be constructed from either SRAM cells or DRAM cells.
In accordance with one embodiment of the present invention, the memory controller operates as follows. If an external write access hits the write buffer, the memory controller causes external data to be written to the write buffer. If an external write access misses the write buffer, the memory controller causes data to be retired from the write buffer to one of the memory banks through a first port. If an external write access misses the write buffer, the memory controller causes external data to be written to one of the memory banks through a second port. If an external write access hits the write buffer, the memory controller enables a refresh operation in the memory bank addressed by the external write access. If an external write access misses the write buffer, the memory controller delays a refresh operation in the memory bank addressed by the external write access until there is no longer an external access to this memory bank. The memory controller delays a refresh operation in a memory bank when data is being retired from the write buffer to the memory bank.
In this embodiment, the memory controller also stops the retiring of data from the write buffer if an external write access hits the write buffer while data is being retired. The data associated with this external write access is then be written to the write buffer.
If the write buffer and read buffer are implemented together in the same memory device, the memory controller causes data to be read from the write buffer when an external read access hits the write buffer and misses the read buffer. Simultaneously, the memory controller causes the data read from the write buffer to be written to the read buffer.
In another embodiment of the present invention, a central refresh timer periodically asserts a refresh request signal. Daisy-chained connections are provided between access control circuits of the memory banks, such that the daisy-chained connections sequentially pass the refresh request signal to the access control circuits in response to a clock signal. A central refresh address generator generates a refresh address, which is provided to all of the memory banks in parallel. The refresh address generator increments the refresh address each time the refresh signal is asserted.